The NTE is a monolithic 4-line-toline decoder in a Lead DIP type The NTE is fully compatible for use with most other TTL and DTL circuits. MOS technology. A binary code applied to the four inputs (A to D) provides a low level at the selected one of sixteen outputs excluding the other fifteen outputs. SNN .. of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration.
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These demultiplexers are ideally suited for implementing high-performance memory decoders. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low.
Each of the 16 outputs can be connected through a resistor and then through an LED to serve as a simple 16 LED controller. Rather than providing only a single enable, both pins are used. Each or these 4-line-toline decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. That is, for an input ofthe 0 output is selected, and it is driven low.
Since the ouputs are active low, NAND gates do the job. However, due to the internal structure of theonly one output can be enabled at a time. If you wanted to generate a 1 of demultiplexer, you could use 16 s looking at the 4 least significant bits, while a single would look at the 4 most significant bits, with one ouput going to each of the other 16 s.
Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use the NAND gates here? There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package I don’t recall seeing 22 pin DIP packages.
4 to 16 decoder logic diagram – Electrical Engineering Stack Exchange
Download the datasheet below for a more comprehensive summary. When 7415 strobe input is high, all outputs are high. Please consider dataaheet those questions you found useful like this one by clicking the arrow pointing up near the answer vote datashest which is in turn above the checkbox you clicked to accept this question.
The active-low output is just how the design for that specific decoder was carried out – there is also active-high varieties. If you want to know exactly what is going on then draw out the truth table, but it is unlikely their function will make much sense to you.
74154 Datasheet PDF
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Email Required, but never shown. Sign up or log in Sign up using Google. The active-low enable inputs allow cascading of demultiplexers over many bits.
First, the inversion of the outputs simply means that the output is active low. The person who took time to answer the question will appreciate that. So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24? Sign up using Facebook. Sign up using Email and Password.
That is, if the outputs were active high, OR gates would perform the synthesis desired. As for the NAND gates, there is a function being implemented in which the gates are there to realize it.
All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design. And why are there 2 of them, you ask? My first question is more important This chip is often used in demultiplexing applications, such as digital clocks, LED matrices, and other graphical outputs.
4 Line to 16 Line Demultiplexer / Decoder
The LED can be chosen at random by the status of the 4 line selector inputs. For example, if the target application requires 16 7-segment Dataeheet displays, but your microcontroller only has 4 lines to select which display is active, this chip 74LS would provide a very effective method of essentially multiplying you selecting lines by a 4 times.
Many TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs. According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs.